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AMD shows newest Radeon Instinct MI60 graphics chips for data centers

Advanced Micro Devices unveiled its Radeon Instinct MI60 graphics processing unit (GPU) for the data center. It promises 1.25 times performance and twice the transistor density of the previous generation. David Wang, senior vice president of engineering in the Radeon Technologies Group, made the announcement at AMDs press and analyst day in San Francisco. He said it can deliver up to 7.4 teraflops of 64-bit floating point peak performance. The new Vega-based GPUs debuting later this year will be built on a 7-nanometer manufacturing process. AMD also described its Zen 2 architecture for new families of central processing units (CPUs) coming in 2019. The GPUs in the cloud will be useful for cloud gaming, virtual desktops and workstations, machine learning, and high-performance computing, Wang said. The total available market is $12 billion by 2021, Wang said. This is the worlds first 7-nanometer GPU, Wang said. It has 13.2 billion transistors, or twice the density of the previous generation, and 1.25 times the performance. It is the worlds fastest floating point 64 and floating point 32 PCIe GPU, he said. AMD will also have an MI50 version GPU available. One Epyc central processing unit (CPU) can connect without bridges to four Radeon Instinct GPUs via the Infinity fabric. The chip also has a third generation of AMDs hardware virtualization, so many users can use a single GPU. This is really our differentiation, and it comes for free, Wang said. In the data center, the GPU can handle machine learning tasks. AMD is releasing ROCm 2.0 open source software for machine learning tasks. Supporters include Baidu, which is using AMD tech. On one benchmark, AMDs MI60 GPU is 8.8 times faster on the DGEMM benchmark than the previous generation 14-nanometer MI25 GPU. On Resnet-50 image processing, it is 2.8 times faster. Wang claimed that AMDs chip can acheive comparable performance to Nvidias Tesla V100 PCIe rival chip. More significant, noted analyst Kevin Krewell of Tirias Research, is that AMDs die size (size of the chip) is less than half the size of the Nvidia chip. That translates into lower costs and lower prices. Peter McGuinness, CEO of startup Highwai, showed how the chip can be used to produce simulated worlds for machine learning, using massive data sets. He showed in real-time how the AMD chip can be used to process data from a self-driving car in real-time, simulating what would be necessary for a car moving down a street. The AMD Radeon Instinct MI60 chip is expected to ship to data center customers by the end of 2018, and the AMD Radeon Instinct MI50 accelerator is expected to begin shipping by the end of the first quarter of 2019. Wang also teased a MI Next chip coming in the future with software compatibility to previous chips. Patrick Moorhead, analyst at Moor Insights & Strategy, said, AMD moved the ball down the field from a hardware perspective with Instincts 7-nanometer design. I am impressed with its one terabyte per second memory bandwidth, ganging with Epyc and Infinity Fabric, and density. I believe its degree of success will be directly related to it uptake of ROCm 2.0 software into customers workflow. AMD Radeon has always had good hardware and it takes hardware, software plus go-to-market to fully move the needle.

AMD’s ‘Rome’ Epyc module will have 64 Zen 2 cores and 2X performance

Advanced Micro Devices said that its next-generation Epyc server chip module, code-named Rome, will have 64 cores based on the Zen 2 architecture. It will also have twice the performance per central processing unit socket as the previous generation, and it will have four times the floating point performance per socket. Rome will consist of eight chips, with eight cores per die, all glued together in a multichip module with accompanying input-output functions — in a single socket. Lisa Su, CEO of AMD, said that the new chip module will debut next year with a 7-nanometer manufacturing process (where the circuits are seven billionths of a meter wide). Rome will have eight 7-nanometer cores per die (or chip), plus a 14-nanometer input/output die. It is the best datacenter processor in the industry, said Su, speaking onstage at the AMD press and analyst day in San Francisco. We are absolutely on track to debut Rome in 2019. This is our space. This is where we lead. The input-output chip will be made with a 14-nanometer manufacturing process. Su and AMD senior vice president Forrest Norrod showed a demo of Rome executing a benchmark. It completed the test in 28 seconds, in comparison to 30 seconds for an Intel two-socket solution with the Intel Xeon Scalable 8180M. Thats a pretty impressive result, said Bob ODonnell, analyst at TECHnalysis Research. The Rome module will have Zen 2 cores, which are based on the second-generation architecture of the Zen platform that AMD introduced in the spring of 2017. Those Zen chips could execute 52 percent more instructions per clock cycle than the previous generation, and Su said that the Rome chips will beat that measure. Zen 2 chips are sampling today at 7-nanometer manufacturing, compared to the shipping 14-nanometer Zen processors that debuted in 2017. Zen 3 is on track to debut on 7-nanometer in 2020. AMD is using TSMC, the chip contract manufacturer, to make its 7-nanometer chips. Intel, meanwhile, has delayed its equivalent chips, dubbed 10-nanometer but at the same technology level, until late 2019. Zen 2 can get twice the throughput thanks to better branch prediction, or predicting what kind of processing will be necessary for the next computation. It also has better 256-bit load/store floating point processing, or double the previous generation. Zen 2 will also have stronger built-in security, where data can be fully encrypted as it is transferred to memory. Norrod said that Epyc adoption can lead to 45 percent lower total cost of ownership (TCO) compared to Intel-based systems. He said that comes as a result of lower admin, licensing, hardware, and space costs. Pete Ungaro, CEO of Cray, said onstage that his companys upcoming Shasta supercomputer will use AMD Epyc processors. The machine will be made for government agencies such as the Lawrence Berkeley National Laboratory and will run at 100 petaflops. Patrick Moorhead, analyst at Moor Insights & Strategy, said he thinks the large multichip modules are the future of entire chip industry. AMD called the chip components within this package chiplets. As for Rome, he said, AMD is showing yet again its commitment to a very aggressive product improvement roadmap. With Rome, AMD is changing everything. It is changing its system-on-chip architecture to 7-nanometer chiplets with an improved Infinity Fabric, doubling cores per socket, doubling bandwidth per socket, adding PCIe 4.0 and improving core and FPU capabilities. He added, AMD says this will deliver an impressive 2X performance per socket and 4X on floating point unit (FPU) per socket. With all these improvements, AMD made Rome socket-compatible with Naples, which should accelerate uptake with [computer makers] and ultimately, end customers. As AMD has delivered on its promises the last two years, I have little doubt AMD will deliver on-time, at quality.