Advanced Micro Devices unveiled its Radeon Instinct MI60 graphics processing unit (GPU) for the data center. It promises 1.25 times performance and twice the transistor density of the previous generation. David Wang, senior vice president of engineering in the Radeon Technologies Group, made the announcement at AMDs press and analyst day in San Francisco. He said it can deliver up to 7.4 teraflops of 64-bit floating point peak performance. The new Vega-based GPUs debuting later this year will be built on a 7-nanometer manufacturing process. AMD also described its Zen 2 architecture for new families of central processing units (CPUs) coming in 2019. The GPUs in the cloud will be useful for cloud gaming, virtual desktops and workstations, machine learning, and high-performance computing, Wang said. The total available market is $12 billion by 2021, Wang said. This is the worlds first 7-nanometer GPU, Wang said. It has 13.2 billion transistors, or twice the density of the previous generation, and 1.25 times the performance. It is the worlds fastest floating point 64 and floating point 32 PCIe GPU, he said. AMD will also have an MI50 version GPU available. One Epyc central processing unit (CPU) can connect without bridges to four Radeon Instinct GPUs via the Infinity fabric. The chip also has a third generation of AMDs hardware virtualization, so many users can use a single GPU. This is really our differentiation, and it comes for free, Wang said. In the data center, the GPU can handle machine learning tasks. AMD is releasing ROCm 2.0 open source software for machine learning tasks. Supporters include Baidu, which is using AMD tech. On one benchmark, AMDs MI60 GPU is 8.8 times faster on the DGEMM benchmark than the previous generation 14-nanometer MI25 GPU. On Resnet-50 image processing, it is 2.8 times faster. Wang claimed that AMDs chip can acheive comparable performance to Nvidias Tesla V100 PCIe rival chip. More significant, noted analyst Kevin Krewell of Tirias Research, is that AMDs die size (size of the chip) is less than half the size of the Nvidia chip. That translates into lower costs and lower prices. Peter McGuinness, CEO of startup Highwai, showed how the chip can be used to produce simulated worlds for machine learning, using massive data sets. He showed in real-time how the AMD chip can be used to process data from a self-driving car in real-time, simulating what would be necessary for a car moving down a street. The AMD Radeon Instinct MI60 chip is expected to ship to data center customers by the end of 2018, and the AMD Radeon Instinct MI50 accelerator is expected to begin shipping by the end of the first quarter of 2019. Wang also teased a MI Next chip coming in the future with software compatibility to previous chips. Patrick Moorhead, analyst at Moor Insights & Strategy, said, AMD moved the ball down the field from a hardware perspective with Instincts 7-nanometer design. I am impressed with its one terabyte per second memory bandwidth, ganging with Epyc and Infinity Fabric, and density. I believe its degree of success will be directly related to it uptake of ROCm 2.0 software into customers workflow. AMD Radeon has always had good hardware and it takes hardware, software plus go-to-market to fully move the needle.
AMD is making the most of TSMC's 7nm process advantage over Intel. AMD today charted out its plans for the next few years of product development, with an array of new CPUs and GPUs in the development pipeline. On the GPU front are two new datacenter-oriented GPUs: the Radeon Instinct MI60 and MI50. Based on the Vega architecture and built on TSMC's 7nm process, the cards are aimed not primarily at graphics (despite what one might think given that they're called GPUs) but rather at machine learning, high-performance computing, and rendering applications. MI60 will come with 32GB of ECC HBM2 (second-generation High-Bandwidth Memory) while the MI50 gets 16GB, and both have a memory bandwidth up to 1TB/s. ECC is also used to protect all internal memory within the GPUs themselves. The cards will also support PCIe 4.0 (which doubles the transfer rate of PCIe 3.0) and direct GPU-to-GPU links using AMD's Infinity Fabric. This will offer up to 200GB/s of bandwidth (three times more than PCIe 4) between up to 4 GPUs. The cards will support a wide range of data types for computation; for neural networks and machine learning, there are half-precision 16-bit floating point and 4- and 8-bit integer support; for HPC workloads, there's single (32-bit) and double (64-bit) precision floating point. AMD claims that the MI60 will be the fastest double-precision accelerator at up to 7.4TFLOPS, with the MI50 not far behind at 6.7TFLOPS. The cards also include built-in support for virtualization, allowing one card to be securely shared between multiple virtual machines. This makes it easier for cloud operators to offer GPU-accelerated virtual machines. The MI60 will ship to datacenter customers by the end of the year; MI50 is coming a little later but should be available by the end of Q1 2019. On the CPU side of things, AMD talked extensively about the forthcoming Zen 2 architecture. The goal of the original Zen architecture was to get AMD, at the very least, competitive with what Intel had to offer. AMD knew that Zen would not take the performance lead from Intel, but the pricing and features of its chips made them nonetheless attractive, especially in workloads that highlighted certain shortcomings of Intel's parts (fewer memory channels, less I/O bandwidth). Zen 2 promises to be not merely competitive with Intel, but superior to it. Key to this is TSMC's 7nm process, which offers twice the transistor density of the 14nm process the original Zen parts used. For the same performance level, power is reduced by about 50 percent, or, conversely, at the same power consumption, performance is increased by about 25 percent. TSMC's 14nm and 12nm processes both trail behind Intel's 14nm process in terms of performance per watt, but with 7nm, TSMC will take the lead. Zen 2 will also address certain weak aspects of the original Zen. For example, the original Zen used 128-bit data paths to handle 256-bit AVX2 operations; each operation was split into two parts and processed sequentially. In workloads using AVX2, this gave Intel, with its native 256-bit implementation, a huge advantage. Zen 2 doubles the floating-point execution units and data paths to be 256-bit, doubling the bandwidth available and greatly improving the performance of this code. For integer workloads, branch prediction and prefetching have been made more accurate and some caches enlarged. Zen 2 will also offer improved hardware protection against some variants of the Spectre attacks. The original Zen used a multichip module design. Chips used one, two, or four dies (for Ryzen, first-generation Threadripper, and Epyc/second-generation Threadripper, respectively) all put together into a single package. Each die had two Core Complexes (blocks of four cores), two memory controllers, some Infinity Fabric links (for connections between dies), and some PCIe channels. This made it straightforward for AMD to scale from the single-die, 8-core/16-thread Ryzen up to the 32-core/64-thread Epyc. Zen 2 is taking a very different approach, albeit one that still uses a multichip design. Instead of having each die contain CPUs, memory controllers, and I/O, the new design splits up the different roles. There will be a single 14nm I/O die, with eight memory controllers, eight Infinity Fabric ports, and PCIe lanes, and then a number of 7nm "chiplets" containing only CPUs and Infinity Fabric. This new approach should remedy some of the more awkward aspects of the original Zen; for example, there is a significant latency overhead when a core on one Zen die has to use memory from another die. With the Zen 2 design, memory latency should become much more uniform. AMD says that Zen 2 is sampling now, with processors due to hit the market in 2019. Zen 3, using an enhanced version of the 7nm process, is currently "on track" and likely to land in 2020, and Zen 4, on a more advanced process, is currently in the design stage.